This application claims priority to an application entitled xe2x80x9cIterative Decoder and Iterative Decoding Method for Communication Systemxe2x80x9d filed in the Korean Industrial Property. Office on Dec. 31, 1998 and assigned Ser. No. 98-62709, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates generally to a receiver in a communication system, and in particular, to a device and method for decoding an input signal.
2. Description of the Related Art
A transmitter in a radio communication system such as a satellite system, or a system using W-CDMA or CDMA 2000, can use a forward error correction code to ensure reliable data transmission. The receiver subjects the received data to iterative decoding, which feeds back the output of a component decoder to the input for decoding. The component decoder outputs not a hard decision signal, like a high (+1) or low (xe2x88x921) signal, but a soft value (e.g., 0.7684,-0.6432, . . . ).
This interleaved sequence is input to a second component decoder, which decodes it. An iterative decoder is composed of at least two component decoders. An interleaver between the component decoders permutes the bit sequence of a frame output from a first component decoder. When the decoded interleaver signal is output for feedback to the first component decoder, a deinterleaver rearranges the bits of the decoded interleaved signal in their original order.
The turbo decoder is a preeminent example of iterative channel decoders. Iterative decoders, such as a turbo decoder, increase their error correction performance by many iterations of decoding.
In the conventional iterative decoding method, data decoding occurs a predetermined number of times without checking whether errors have been generated during the iterative decoding. Errors are checked by subjecting the deinterleaver output to hard decision decoding.
In the case of typical iterative decoding, however, the greatest decoding gain is generally obtained during the first two or three decodings, though this varies with the channel environment. In fact, error correction performance resulting from iterative decoding may rapidly drop after a number of decodings. Furthermore, after a certain number of iterative decodings, system resources, like power consumption and processing delay, are being dissipated for a marginal performance gain. For example, a certain number of iterative decodings can cause signal oscillations due to the feedback characteristics of the iterative decoder. In other words, perfectly error-corrected data can actually begin to generate errors as decoding is repeated.
The problem of the threshold number (the iteration number beyond which errors may be generated) of iterative decodings is overcome by appropriately picking the number of decoding iterations. If it can be determined that the probability that all errors have been correct is approximately 1 the iterative decoder need not decode, the input signal any further. Whether decoding is completed can be determined in several ways. One of them is to check errors utilizing a CRC ,(Cyclic Redundancy Code) check of decoder output. Because the CRC check does not alter the information to be transmitted, it is impossible, for the CRC check to generate errors in the decoded data. However, the challenging task for a system designer is to limit the additional processing delay that would be involved in performing an error check in the iterative decoding scheme. Therefore, a need exists for a device and method of limiting the number of iterations in an iterative decoder by performing an error check on the decoded data without incurring undue processing delay.
It is, therefore, an object of the present invention to provide an iterative decoder and iterative decoding method for dynamically determining the appropriate number of decoding iterations of received data.
It is another object of the present invention to provide an iterative decoder and iterative decoding method, in which the output of each component decoder is checked for the presence or absence of errors while decoding.
It is a third object of the present invention to provide an iterative decoder and iterative decoding method, in which the output of each component decoder is checked for the presence or absence of errors while decoding and which stops decoding immediately if no errors are detected.
It is a fourth object of the present invention to provide an iterative decoder and iterative decoding method, in which the processing delay is minimized during an error check of each component decoder output during decoding.
It is a fifth object of the present invention to provide an iterative decoder and iterative decoding method, in which the output of each component decoder is checked for the presence or absence of errors while decoding and which stops decoding immediately if no errors are detected, in a continuous mode
It is a sixth object of the present invention to provide an iterative decoder and iterative decoding method, in which the output of each component decoder is checked for the presence or absence of errors at the time when the output of the component decoder is arranged in the original order and stops decoding immediately if no errors are detected, in a continuous mode.
It is a seventh object of the present invention to provide an iterative decoder and iterative decoding method, in which, when each component decoder is operated in a continuous mode, one frame is subjected to an error check simultaneously with completion of decoding that one frame in a first component decoder and decoding is immediately stopped if no errors are detected.
Briefly, these and other objects are achieved by providing an iterative decoder. In the iterative decoder, a first adder has a first port for receiving information symbols and a second port; a first component decoder is coupled to the first adder, for receiving first parity symbols and decoding the information symbols using the first parity symbols and an output signal of the first adder; a first subtractor has a third port for receiving the output of the first component decoder, and a fourth port; an interleaver coupled to the output of the second adder, for interleaving the decoded information symbols received from the first component decoder; a second component decoder receives the output of the interleaver and second parity symbols and decodes the information symbols of the interleaver output using the received signals; a deinterleaver deinterleaves the output of the second component decoder; a second subtractor has a fifth port for receiving the output of the deinterleaver and a sixth port for receiving an inverted output of the second adder, the output of the second subtractor connected to the second port and an inverted output of the second subtractor connected to the fourth port; a hard decision device converts the decoded symbols received from the first component decoder to binary information bits; an error detector checks for errors in the binary information bits received from the hard decision device and generates a no error signal if no errors are detected; and an output buffer stores the binary information bits received from the hard decision device and outputs the stored binary information bits in response to the no error signal.
In the iterative decoding method for an iterative decoder having a predetermined maximum number of iterations, the method includes the steps of: iterative decoding an input frame signal; checking for errors in the decoded frame data before the predetermined number of iterations are completed; and outputting the decoded frame if no errors are detected.